Most digital communication within the switched, telecommunications networks is limited to 64 kilobits per second due to the constraints imposed by existing switching systems and transmission facilities. In specific applications requiring greater bandwidth, several narrowband channels are combined to form a wideband channel, sometimes referred to as an N.times.DS0 channel, where DS0 refers to a 64 kilobits per second channel and therefore an N.times.DS0 channel is an integer multiple of 64 kilobits per second. A problem occurs when the data from grouped channels is not switched through a switching system in the same order that the data is received. This occurs when a time slot interchanger of the switching system causes some, but not all, of the time slot data of a given time division frame to be delayed and combined with the time slot data of another time frame. One solution to this problem is to provide double-buffered time slot interchangers where all the data from one frame is written into a first buffer while at the same time data is read out from a second buffer that was stored therein during the previous frame. The reading and writing of the first and second buffers alternates every frame. This solution works well but adds both the cost of the additional memory and one frame of transmission delay for each double-buffered time slot interchanger. In addition, the problem remains for the large number of existing switching systems with only single-buffered time slot interchangers.